The present application relates generally to an improved data processing apparatus and method, and more specifically to an apparatus and method for providing a read- and write-aware cache.
A cache is used to speed up data transfer and serve as staging areas for data. Memory caches speed up instruction execution, data retrieval and data updating, and their contents are constantly changing. A memory cache, or “CPU cache,” is a memory bank that bridges main memory and the central processing unit (CPU). A memory cache is faster than main memory and allows instructions to be executed and data to be read and written more quickly. Instructions and data are transferred from main memory to the cache in fixed blocks, known as cache “lines.”
Not all parts of a large cache can be accessed from a given point (such as a CUP) with the same latency. Non-uniform cache architectures (NUCA) have therefore arisen as an emerging cache architecture for large cache designs. In a NUCA design, the cache is partitioned into multiple banks that have different access delays from an access point (such as a CPU) due to where the banks are placed, differing wire delays and latencies. Intelligently managing the differing latency characteristics found in NUCA improves the performance of memory systems.
In a Dynamic NUCA (D-NUCA) design, a line is typically placed into any one of the banks. D-NUCA may use non-traditional cache placement and data movement policies to put frequently accessed data in closer banks. A first bank is defined as “closer” than a second bank if the first bank ahs a shorter latency to the processing unity than the second bank. Thus data may be accessed more quickly from the closer bank.